1. Field of the Invention
The present invention is a method and apparatus relating to integrated circuit devices, and more particularly to a method and apparatus for precharging an internal data bus of an integrated circuit.
2. Description of the Prior Art
Integrated circuits often include an internal bus consisting of parallel signal lines to which various functional circuitry is connected. In particular, memory circuits, which are organized into blocks of memory cells, often communicate data utilizing an internal data bus. The internal data bus in memory circuits accesses the blocks of memory cells located within the memory chip.
Modern memory circuits are required to operate at high speeds while possessing the highest density possible. In such memories, the series resistance and parasitic capacitance of relatively long signal lines in an internal data bus becomes a significant factor in the operating performance of the device. The signal lines in a data bus switch from one state to another as various memory cells are accessed, and any parasitic capacitance affects the time required for the signal line to switch. The inherent resistance of the signal lines also increases the time constant of the switching. In addition, as the density of a memory chip increases, the cross-sectional area of a signal line may decrease, increasing the resistance. The increased number of signal lines also tends to increase the parasitic capacitance in the lines.
Currently, to increase the efficiency of reading a stored state in a memory cell, the signal lines in a data bus are precharged to a pre-selected voltage. The stored state of each memory cell is then communicated to the signal lines utilizing bit lines. However, the bit lines are shorter and may have less than one-third of the capacitance of the data bus. Hence, the precharged stage of the signal lines is often the limiting factor in the cycle time for the device. If the signal lines have not been completely precharged, the digital value of the stored state of the memory cell may be incorrectly detected, or the detection process may be delayed.
As presently known in the art, signal lines in an internal data bus are precharged to a pre-selected voltage before the stored state of a memory cell is communicated to the signal lines. However, the parasitic capacitance and inherent resistance of the signal lines in an internal bus can create a large RC time constant. A large time constant increases the time required to completely precharge the signal lines. This delay is especially problematic in memory chips having long internal busses used to access memory cells. Thus, a short precharge stage of a signal line in a memory access cycle is needed.
Therefore, a method and apparatus is needed which decreases the time necessary for the precharge stage of the bus signal lines, prior to application of a stored memory state. Furthermore, the method and apparatus must not affect the density of the integrated circuit and increase the manufacturing cost of the integrated circuit.